Online MIPS Assembler for (System)Verilog 

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    <p>This is a modified version of the online MIPS assembler found at <a href="https://github.com/bilkentCraps/mips">https://github.com/bilkentCraps/mips</a>. The main differences
    are as follows:</p>
    <p>
        <ol>
            <li>This assembler is able to parse hexadecimal and binary numbers</li>
            <li>The <code>adr</code> field of J-Type instructions are interpreted as memory addresses instead of line numbers</li>
            <li>This assembler supports using the <code>shamt</code> field for R-type instructions</li>
            <li>If the default instruction definitions are used, the immediate used in the <code>beq</code> instruction is interpreted as an offset from the next line (that is, <code>beq $zero, $zero, -1</code> results in an infinite loop)</li>
        </ol>
    </p>
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