Online MIPS Assembler for (System)Verilog

This is a modified version of the online MIPS assembler found at https://github.com/bilkentCraps/mips. The main differences are as follows: This assembler is able to parse hexadecimal and binary numbers The adr field of J-Type instructions are interpreted as memory addresses instead of line numbers This assembler supports using the shamt field for R-type instructions If the default instruction definitions are used, the immediate used in the beq instruction is interpreted as an offset from the next line (that is, beq $zero, $zero, -1 results in an infinite loop) The left textbox contains the instruction definitions, the middle textbox contains the assembly code, and the right textbox contains the code to paste inside the imem module
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Tree Example Generator

This webpage is intended for practicing insertion and removal for various data structures (BSTs, AVL trees, 2-3-4 trees etc.). However, it can also be used for generating a specific amount of unique random integers in a given range (just uncheck the option named Allow removal). Note: Since the numbers are generated completely at random, there are no guarantees on an example sequence of operations being “interesting” or including all the edge cases for the given data structure.
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